Programmable logic devices (PLDs) are a well-known class of digital integrated circuits that may be programmed by a user (e.g., a circuit designer) to perform specified logic functions. Complex PLDs typically include an array of configurable logic elements that are programmably interconnected to each other and to programmable input/output blocks via some form of programmable interconnect. This collection of configurable logic may be customized by loading configuration data into internal configuration memory cells that define how the logic elements, interconnect, and input/output blocks are configured.
FIG. 1 (prior art) is a block diagram depicting one form of complex PLD (CPLD) 100, which includes configurable logic and interconnect 105, configurable input/output blocks 110, input/output pins 115, and an array of non-volatile memory 120. CPLD 100 is personalized by loading non-volatile memory 120 with configuration data. CPLD 100 then transfers the contents of memory 120 into static random-access memory cells (not shown) within configurable logic and interconnect 105 and input/output blocks 110 when CPLD 100 is powered up.
FIG. 2 (prior art) depicts a non-volatile memory array 200 typical of the type employed in non-volatile memory 120 of FIG. 1. Memory array 200 includes rows [r] and columns [c] of identical three-transistor (3T) EEPROM memory cells 205[r,c], wordlines wL[r] and control-gate lines cgL[r] connected to the rows of memory cells 205, and read bitlines rBL[c] and configuration bitlines CBL[c] connected the columns of memory cells. Memory array 200 additionally includes a virtual ground terminal VGND connected to each memory cell 205[r,c].
Each memory cell 205[r,c] includes an access transistor 210, a configuration transistor 215, a memory transistor 220, a programming dielectric 225, and a capacitor 230. Memory cells 205[r,c] can be programmed or erased by moving charge to and from the floating-gate node FG through programming dielectric 225, typically a so-called “tunnel oxide,” to change the threshold voltage of transistor 220. The following discussion focuses on memory cell 205[0,0]: the remaining memory cells are identical.
Memory cell 205[0,0] is read by forward biasing access transistor 210 using wordline wL0 and applying a read voltage, typically supply voltage VDD, to control-gate line cgL0. If the threshold voltage of transistor 220 is low (i.e., cell 205[0,0] is programmed), transistor 220 will conduct (i.e., provide a low impedance), connecting read bitline rBL0 to ground potential via access transistor 210. A sense amplifier (not shown) connected to read bitline rBL0 produces an output voltage representative of a first stored logic level, typically a logic zero. If, on the other hand, the threshold voltage of transistor 220 is high (i.e., cell 205[0,0] is erased), transistor 220 will not conduct (i.e., provide a high impedance) with supply voltage VDD applied to control-gate line cgL0, so read bitline rBL0 will remain isolated from ground potential. The sense amplifier connected to read bitline rBL0 thus produces an output voltage representative of a second stored logic level, typically a logic one.
To erase memory cell 205[0,0], ground potential is applied to configuration bitline cBL0 and a programming voltage VPP greater than supply voltage VDD is applied to electrons to floating gate node FG through oxide 225, raising the threshold voltage of transistor 220. To program memory cell 205[0,0], ground potential is applied to control-gate line cgL0 and programming voltage VPP is applied to wordline wL0 and configuration bitline cBL0. This biasing arrangement moves electrons away from floating gate node FG through oxide 225, reducing the threshold voltage of transistor 220.
Memory array 200 reliably stores configuration data, and CPLDs have proven valuable for many applications. Unfortunately, the non-volatile memory can occupy about 20% or more of the area of a CPLD. Because area is key factor in the cost of manufacturing integrated circuits, the inclusion of non-volatile memory considerably increases the expense of producing CPLDs and other circuits that employ non-volatile memory. There is therefore a need for more area-efficient non-volatile memory.